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MXED401
200-Column Cholesteric LCD Driver FEATURES:
* * * * * * * * * * * * * Drives Reflective-type Liquid Crystal Displays Black-White or Gray-Scale Cholesteric LCD (ChLCD) Compatible 200 Output Channels, Cascadeable 192-Channel Mode Token-Based Bi-directional Data Transfer 6-Bit Data to support 64-Level Gray-Scale 2V to 7V panel drive 4mA Minimum Source/Sink at 7VOutput Levels 2.5V to 5V logic supply 26 MHz clock frequency 4mA Minimum Source/Sink at 7V Output Levels Gold-Bumped Die @ 60 micron Output Pitch
OVERVIEW:
Clare introduces the MXED401, targeted for the emerging non-volatile reflective LCD market, specifically bi-stable and multi-stable Cholesteric LCD's. The MXED401 supports 200 phase-controlled voltage data outputs. This is the first standard product driver for ChLCD display panels.
FUNCTIONAL DESCRIPTION:
The MXED401 driver functions as a level shifter with a resting state at ground potential. Proper operation of the logic enables gray-scale capability. The output is a 128 Counter Clock (CCLK) event where each channel is a low resistive switch to external symmetric (with respect to ground) voltage supplies. Proper operation of the logic allows gray scale capability. The output is initially low (MV4) from one to sixty-four CCLK times, then continuously high (PV4) for sixty-four CCLK times, returning low for the balance of the 128 CCLK cycle (before returning to its quiescent value (VSS2)). The data driver chip is manufactured in a high voltage (30 V) CMOS process and is available in gold-bumpeddie form. The Token Bit Shift Register is used to control data latch timing for the Temporary Storage Register. A token bit (initialized by SRIN input) is transferred sequentially among the 200 possible (internal) outputs of the Shift register. This allows data to fill the Temporary Storage Register to in a Right to Left fashion. When the Temporary Register is filled its contents may be transferred to the Output Storage register via the LAT input. Output phase control is then accomplished by the Pulse Phase Shift Logic, data then passes to the High Voltage Translator unit to control the three output switches associated with each column output driver.
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January 29, 2003
MXED401
FIGURE 1 - MXED401 BLOCK DIAGRAM
0197 0198 0199
00
PV4 VSS2 MV4 3 OUT0 1 CCLK CRB INV 6 LAT 6 D(5:0) 1 SCLK SHR SEL200 SRIN REN REG5V
01
02
3-LEVEL OUTPUT STAGE 3 3
HIN=(PV4 - 4.0V) XIN=4.75 TO 11.0V) 3 3 3
HIN XIN
LOGIC TO FORCE OUTPUT TO VSS2 AND HV TRANSLATOR INTERFACE 1 1 PULSE PHASE SHIFT LOGIC 6 6 OUTPUT STORAGE REGISTER (6 BITS X 200) 6 6 TEMPORARY STORAGE REGISTER (6 BITS X 200) 1 1 TOKEN BIT SHIFT REGISTER (1 BIT X 200) 1 1 1 VDD1 VSS1 SLIN 5.0 VOLT REGULATOR TEST CIRCUITRY PV4 - 4.0V REGULATOR HEN HREF 6 6 6 6 6 6 1 1 1
VPCAS RB
NON DON PON
VMCAS
FLYLO
FLYHI
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MXED401 DATA SHEET Table of Contents
FEATURES ....................................................................................................................1 OVERVIEW ....................................................................................................................1 FUNCTIONAL DESCRIPTION .....................................................................................1 FIGURE 1 - MXED401 BLOCK DIAGRAM .................................................................2 TABLE 1 - ABSOLUTE MAXIMUM RATINGS ............................................................4 TABLE 2 - OPERATING CONDITIONS .......................................................................4 CIRCUIT DESCRIPTION ..............................................................................................5 FIGURE 2 - REGULATOR BLOCK DIAGRAM ...........................................................5 FIGURE 3 - EXAMPLE USING ON-CHIP REGULATOR ............................................5 FIGURE 4 - EXAMPLE USING EXTERNAL BIAS ......................................................5 FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS.................................................6 FIGURE 6 - HREF BLOCK DIAGRAM ........................................................................7 FIGURE 7 - EXAMPLE USING ON-CHIP HREF BIAS ...............................................7 FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS ..........................................7 FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH .....................................8 FIGURE 10 - ...................................................................................................................9 FIGURE 11 - ...................................................................................................................9 FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM ......................................... 10 FIGURE 13 THROUGH 15 - PHASE DETECTOR WAVEFORM EXAMPLES ........11 ELECTRICAL SPECIFICATIONS ........................................................................12-14 TABLE 3 - COLUMN DRIVER IC DESIGNATION TABLE ...................................... 15 TABLE 6 - AC CHARACTERISTICS ........................................................................ 16 FIGURE 16- OUTPUT WAVEFORM DEFINITION ................................................... 16 MECHANICAL SPECIFICATIONS ............................................................................ 17 DIE SPECIFICATIONS ............................................................................................... 17 FIGURE 17 - DIE DIMENSIONAL DRAWING .......................................................... 18 TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER) ................................. 19 TABLE 5 - TRUTH TABLE (DATA LATCH) .............................................................. 19 ORDERING INFORMATION ...................................................................................... 20
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage VDD1 Supply voltage PV4 Supply voltage MV4 X IN i n p u t H IN i n p u t Logic input levels S torage temperature M in . -0.3 -0.3 -9.0 -0.3 PV4-6.0 -0.3 -65 Max. 7.0 9.0 +0.3 12.0 PV4+0.3 VDD1 + 0.3 150 U n it V V V V V V C e lsius
OPERATING CONDITIONS
Parameter Supply voltage VDD1 Supply Voltage PV4 Supply Voltage MV4 H IN X IN Te m p e r a t u r e A m b i e n t M in . 2.5 2 -7 PV4-4.2 4.75 -20 Max. 5.5 7 -2 PV4-3.8 11 80 V C e lsius U n it V V V
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CIRCUIT DESCRIPTION
Voltage Regulator This product may be operated from supplies as low as 2.5 Volts. The output drive transistors require a voltage of 5.0 volts to 11.0 volts on the XIN pin to assure proper circuit operation. This bias voltage may be developed on the chip or provided by the system designer. When XIN is provided externally, the REN (Regulator ENable) pin is held low, and the FLYHI/FLYLO pins are left unconnected. Systems lacking an available bias may use the on chip voltage regulator. The circuit is enabled by forcing REN high (to VDD1). This will cause an on-chip oscillator/charge pump circuit to operate continuously and output a somewhat regulated 5 volts at pin REG5V. A capacitor (CFLY=0.1uF) is connected between pins FLYHI and FLYLO. A storage capacitor (CHOLD=1.0uF) is required on REG5V. The XIN input is then connected to the REG5V output. The charge pump is capable of driving 18 XIN loads so generally only one or two circuits are used as regulator sources. In systems where more than one regulator circuit is enabled it is forbidden to short their respective HOLD capacitors. Enabling the regulator causes an additional DC current of 65uA (130 uA maximum) to flow from VDD1 to VSS1.
FIGURE 2 - REGULATOR BLOCK DIAGRAM FIGURE 3 - EXAMPLE USING ON CHIP REGULATOR FIGURE 4 - EXAMPLE USING EXTERNAL BIAS
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FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS
HREF Bias Generator The output stage requires a reference supply 3.8 to 4.2 volts lower than PV4 into each HIN input. This may be provided by the system designer or generated on-chip. When HEN is held high, a bias voltage is generated at the HREF output which is (PV4-4.0v). This generated voltage may then be used to supply 6 HIN inputs. The HREF output must be stabilized by connecting a 0.1uF capacitor between HREF and PV4. A separate stabilizing capacitor is required for each HREF used. It is forbidden to connect any HREF pin to another HREF pin. Each enabled HREF output causes an additional DC current of 60uA (130 uA maximum) to flow from PV4 to MV4.
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FIGURE 6 - HREF BLOCK DIAGRAM FIGURE 7 - EXAMPLE USING ON CHIP HREF BIAS FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS
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Data Input Procedure A data synchronization bit is entered into the TOKEN bit shift register via the SRIN (or SLIN) on a rising edge of SCLK. The token bit travels along the complete shift register path in order to control data latching. The internal logic is shown below. Notice the use of the SCLK divider. SCLK frequency is halved inside the IC to keep the current consumption to a minimum. The shift logic modifies the input signals in a manner that requires input data (DAT5:0) to follow the SRIN synchronization bit by 2 SCLK rising edges. Initialization of the system is accomplished via the RB input pin. The 6-bit data word is passed through the output register when pin LAT is LOW. When pin LAT is HIGH data is latched in the output storage register. The inputs SHR and SEL200 are set by the user to control SHift-Right (versus shift left) operation and SELect 200 output configuration (versus 192 output configuration.). When SEL200 is LOW the user ignores the output pads near the edge of the die. That is, ignore outputs O0-O3 and O196O199, use only outputs O4-O195. When SHR is HIGH data is loaded first into the lower number outputs first and completes the load at the higher numbered outputs. For example, with SHR high and SEL200 low the input data will load into register O4 first and complete the cycle by loading O195 on the last clock edge.
FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH
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FIGURE 10 FIGURE 11 -
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Phase Logic and Out0 The circuit has a 7-bit counter that is reset in a synchronous manner via the CRB (Counter-ResetBar) and CCLK (Counter CLK) pins. The counter is "preset" to zero if the CRB pin is low when the CCLK pin rises. Each phase detector output is a 128 CCLK event. The INV pin will be assumed low for the purpose of this discussion. Upon reset (via CRB) the output will be low. The output is always guaranteed to be high continuously for 64 units of the 128 CCLK event. The output is also guaranteed to be low for 64 units of the 128 CCLK events, however, not usually continuously. The input data indicates which event should be completed in order to allow the data to go high. For example, an input data word of zero will cause the output to be low until the first rising edge of CCLK, then high for the subsequent 64 rising edges, then low again for the final 63 clocks. Notice that the output is always initially low for at least one CCLK period. A fifty percent (50%) duty cycle is attained when 63 (2F-HEX) is the input data; resulting in 64 units of low followed by 64 units of high. The INV pin may invert the output from the above discussion. Pin INV must be high in order to produce a 64 unit high followed by a 64 unit low pulse train. The OUT0 (OUTput ZERO) pin will always command all outputs to zero volts potential (via the VSS2 input) irrespective of the individual states of CCLK, CRB or data stored in the output storage register.
FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM
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FIGURES 13 - 15 - PHASE DETECTOR WAVEFORM EXAMPLES
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DC ELECTRICAL CHARACTERISTICS
Parameter Logic supply current Symbol IVDD1 Min Max. 0.01 2.6 6.6 10.0 130 60 150 20 -60 -170 300 300 -450 VDD1-0.3 0.3 VDD1-0.5 0.5 3 -3 +V4-0.02V -0.020V 0.020V PV4+0.02V 3 -3 Unit mA Condition Vdd=2.5V Vdd=2.5V Vdd=3.3V Vdd=5.0V Sclk=0MHz Sclk=26MHz Sclk=50MHz Sclk=50MHz
IDD1 due to REG5V ckt PV4 supply current (DC) PV4 supply current (DC) XIN supply current (DC) MV4 supply current (DC) MV4 supply current(DC) PV4 supply current(AC) XIN current(AC) MV4 supply current(AC) Logic input high voltage Logic input low voltage Logic output high voltage Logic output low voltage Logic input current high level Logic input current low level Output voltage high Output voltage zero Output voltage low
IDDREG IPV4DC1 IMV4DC2 IXINDC IPV4DC1 IPV4DC2 IPV4AC IXINAC IMV4AC VIH VIL VOH VOL IIH IIL VOH VOO VOL
uA uA uA uA uA uA uA uA uA V V V V uA uA
REN=H (no XIN load) HEN:L HEN:H
HEN:L HEN:H CCLK=2.5MHz CCLK=2.5MHz CCLK=2.5MHz
IOH=1mA IOL=-1mA Vinput=VDD1 Vinput=0V Iload=0 Iload=0 Iload=0
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DC ELECTRICAL CHARACTERISTICS (CONT.)
Parameter REG5V fanout HREF fanout Output switch impedance high Output switch impedance zero Output switch impedance low Output switch current high Output switch current sink Output switch current source Output switch current sink Output switch current source Output switch current low Symbol RFO HFO ZOH (1) ZOO (1) ZOL (1) IOH IOOL4 IOOH4 IOOL2 IOOH4 IOL 2 -4 4 -2 4 -4 PV4-0.2V -0.20V 0.20V MV4+0.2V mA mA mA mA mA mA Min Max. 18 8 Unit Condition XIN loads HIN loads Iload=-0.2mA (1) -0.2mA>Iload>0.2mA (1) Iload=0.2mA (1) PV4=7,Vout=-7V Vout=4.0V, OUT0=H Vout=-4.0V,OUT0=H Vout=2.0V, OUT0=H Vout=-2.0V,OUT0=H MV4=-7,Vout=+7V
(1) PV4 = 2V, MV4 = -2V
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AC ELECTRICAL CHARACTERISTICS
Parameter SCLK min pulse width high SCLK min pulse width low SCLK data setup time SCLK data hold time CCLK min pulse width high CCLK min pulse width low CCLK -CRB setup time CCLK -CRB hold time LAT min pulse width high LAT min pulse width low LAT fall after SCLK rise time LAT rise before SCLK rise time Symbol TSPWH TSPWL TSS TSH TCPWH TCPWL TCS TCH TLPWH TLPWL TSS TSH VDD1=>2.5V 15 15 15 15 50 50 25 25 50 50 50 50 VDD1>3.2V 8 8 8 8 25 25 12 12 25 25 25 25 Unit nS nS nS nS nS nS nS nS nS nS nS nS
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COLUMN DRIVER IC DESIGNATION TABLE
Symbol Name O0 to O199 OUT0 CRB CCLK INV LAT D[5:0] SCLK SHR SEL200 VDD1 VSS1 PV4 MV4 SRIN SLIN HIN HEN HREF REN FLYHI FLYLO REG5V XIN VSS2 RB I/O O I I I I I I I I I I/O I/O I I O I O I I Designation Column Drive Output Output Gate (Asynchronous) Counter Clear Signal(synchronous) Pulse Phase Shifter Counter Clock Phase Shift Data Invert Signal Phase Shift Data Latch Strobe Phase Shift Data Token Shift Clock Data Shift Direction Data Output Select 200 or 192 Power Supply For Logic System Logic Ground Power Supply For LC Drive Power Supply For LC Drive Data Synchronization bit Data synchronization bit High Reference input HREF source enable signal High Reference Output Regulator Enable Input Voltage Regulator flying capacitor. Voltage Regulator flying capacitor. Regulated 5 volt output Translator input bias reference Output Driver Ground Master Reset Function H:Vss2 , L:PV4,MV4
L & CCLK Rising Edge: Counter Clear H: Counter Enable L: disable Rising Edge : Count, Max 4MHz L: Normal ,H: Invert (see Fig 14&15) H : Latched, L: Transparent
D(5) : MSB, D(0):LSB Data entered on Rising Edges H: Shift Right, Input is SRIN L: Shift Left, Input is SLIN H: SRIN to O000, (SHR:H) L: SRIN to O004, (SHR:H) 2.5 To 5.5V 0V 7 to 2V -7 to -2V Input for SHR:H, Output for SHR:L Input for SHR:L, Output for SHR:H (PV4-4.0V) (see HREF/HIN also) L: HREF not used , H: Enable HREF (PV4-4.0V)Reference output Enable:H, Disable:L 0.1uF cap to FLYLO when REN:H No connect when REN:L 0.1uF cap to FLYHI when REN:H No connect when REN:L 1.0uF cap to VSS1 When REN:H Bias between +5.0V to +11.0V 0V Reset :L , Normal:H
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TABLE 6 - AC CHARACTERISTICS (See Fig. 16)
Parameter Shift Clk Frequency Count Clk Frequency Rising Time Falling Time Tr Tf Symbol Min Typ. Max. Unit 26 4 5 5 1.0 1.0 25 1 MHz MHz us us Kohm Kohm us us Condition VDD1 = 2.5V VDD1=2.5V SEE FIG. 16 SEE FIG. 16 Iout=200uA Iout=200uA See Section 8 TBD
PV4 Driver PV4Ron Equivalent output resistance MV4 Driver MV4Ron Equivalent output resistance PV4,MV4 Pulse Width Output Delay Time TPV4,TMV4
FIGURE 16 - OUTPUT WAVEFORM DEFINITION
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MECHANICAL SPECIFICATIONS
DIE SPECIFICATIONS Die Dimensions: "X" Dimension "Y" Dimension Thickness Gold Bump Height 12830 m 1760 m 635 m (nominal) 153 m Measured from center of scribe to center of scribe Measured from center of scribe to center of scribe Unthinned (non-back lapped wafer)
Die Materials: Passivation Gold Bump Hardness Wafer Silicon Nitride (SiN) 45-75 HV Silicon (Si)
Note: The active surface is sensitive to light. Cover with an opaque material after assembly.
COORDINATES RELATIVE T O ORIGIN (0, 0) AT MINIMUM PAD CENTER LOCATION
Corners of Scribe Centers Lower Left: Upper Right: X = -115m, Y = -205m X = 12715m, Y = 1555m
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FIGURE 17 - DIE DIMENSIONAL DRAWING
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TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER)
INPUT SHR H H L L SCLK SEL200 Input-Output SRIN Input Input Output Output SLIN Output Output Input Input D(5:0) sequence O0,O1...O198,O199 D(5:0) sequence O4,O5...O194,O195 D(5:0) sequence O199,O198...O1,O0 D(5:0) sequence O195,O194...O5,O4 Data to clock synchronization
Rising Edge H Rising Edge L Rising Edge H Rising Edge L
TABLE 5 - TRUTH TABLE (DATA LATCH)
LAT H L CONDITION Latched Open (Transparent)
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ORDERING INFORMATION
MXED401
Ordering Part Number 14501-00 14526-00 14535-00 14539-00
Package Gold Bumped Die in Waffle Trays Gold Bumped Die in Wafer Form TCP (Tape Carrier Package) please consult factory BGA (typically for prototyping only)
For additional information please visit our website at: www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
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